In the field of semiconductor integrated circuits, input signals have become susceptible to the effects of noise even in digital signal processing circuits owing to increases in scale and speed and use of lower voltages, etc. A method of removing noise in analog fashion and a method of removing noise by digital signal processing have been considered as methods of removing noise from an input signal. Since variations in characteristics occur with the method of removing noise by analog means, removing noise by digital signal processing is preferable if this can be achieved.
FIG. 5 is a block diagram of a conventional digital noise filter circuit described in Patent Document 1, which is cited below. A D-type flip-flop (referred to as a “DFF” below) 12 has a data input terminal D supplied with an input signal Sin, which is a binary signal, via a buffer 10, and a clock input terminal CK supplied with a clock signal CLK. The signal that has been input to the data input terminal D is latched in the DFF 12 at the rising edge of the clock signal CLK, and the latched signal is output via a data output terminal Q. The DFF 12 further has a reset input terminal SAN supplied with a negative-logic reset signal RST. When the reset signal RST falls from “1” to “0,” the output signal of the data output terminal Q is forcibly reset to “1” irrespective of the state of the signal at the data input terminal D, etc. When the reset signal RST subsequently rises from “0” to “1,” a state in which the output signal is changed over in accordance with the state of the signal at the data input terminal D, etc. is attained.
Similarly, DFFs 14, 16 and 32 have respective clock input terminals CK supplied with the clock signal CLK, and with respective reset input terminals SAN supplied with the reset signal RST. An output signal S12 from the DFF 12 is supplied to data input terminal D of the DFF 14, and an output signal S14 from the DFF 14 is supplied to the data input terminal D of the DFF 16. As a result, the signals S14 and S16 are signals obtained by delaying the signal S12 every cycle of the clock signal CLK.
The digital noise filter further includes AND gates 18, 26 and 28, a NOR gate 20, OR gates 22, 30, and an inverter 24. These construct a combinatorial circuit 2. The combinatorial circuit 2 outputs a signal S2 the value of which is set, as indicated by (1) and (2) below, based upon the signals S14, S16 and the output signal Sout of the DFF 32.
(1) If the signals S14, S16 have the same value, then the signal S2 is set to this value.
(2) In a case other than (1), the signal S2 is set to a value the same as that of the output signal Sout.
The signal S2 is latched in the DFF 32 at the rising edge of the clock signal CLK and the latched result is output as a new output signal Sout.
The DFF 12 of the first stage is provided for dealing with a metastable event. Here the term “metastable event” means that the output of the first-stage DFF becomes unstable if the rising edge of the clock signal CLK and a change in the input signal to the DFF overlap. According to Patent Document 1, the first-stage DFF 12 in FIG. 5 is used only for dealing with a metastable event, and the output signals of the DFFs 14, 16 of the following stages are used in the operation performed by the combinatorial circuit 2, as a result of which the effects of a metastable event on the result of the operation can be suppressed sufficiently.
Next, the operation of this conventional digital noise filter circuit will be described. FIG. 6 is a waveform diagram of signals at various portions of the conventional digital noise filter circuit described in Patent Document 1. The clock signal CLK, which has a prescribed period, is assumed to have rising edges at times t0, t1, t2, t18. These times will also be referred to as “clock timing” below. In the illustrated example, the reset signal RST falls to “0” at time t01 and rises to “1” at a subsequent time t21. When the reset signal RST falls, the values that have been latched in DFFs 12, 14, 16, 32 are forcibly reset to “1.” Thereafter, even after the reset signal RST rises to “1,” “1” continues to be latched in the DFFs 12, 14, 16, 32 so long as the input signal Sin is “1.” The output signals of these DFFs are held at “1.”
Next, assume that the input signal Sin falls to “0” at time t31. This “0” signal is latched in the DFF 12 and the signal S12 falls to “0” at the clock timing of time t4. Since the signal S12 is then latched in the DFF 14 at time t5, the signal S14 falls to “0” at time t5, as illustrated.
Next, when the input signal Sin rises to “1” at a subsequent time t51, the “1” signal is latched in the DFF 14 and the signal S14 rises after two rising edges of the clock signal CLK, namely at time t7. Thereafter, and in similar fashion, the input signal Sin changes over at times t71, t81, t101, t121, t131, t141 in the example of FIG. 6. Since the level after the changeover is held until the next clock timing, the level of the signal S14 changes over at the times t9, t10, t12, t14, t15, t16. Further, the output signal S16 of the DFF 16 has a waveform similar to that of the signal S14 and is a signal that has been delayed by one clock cycle with respect to the signal S14.
The operational result based upon the signals S14, S16 and output signal Sout is output as signal S2, and the signal S2 is output as the output signal Sout of the next cycle by being latched in the DFF 32. If the input signal Sin and output signal Sout are compared in FIG. 6, it will be understood that the section of the input signal Sin in which the clock timings generated over the duration in which there is a constant signal level are not more than one (namely the sections in signals S12, S14, S16 in which the constant-level duration is one clock cycle) has been set to a signal level identical with that of the section before and after in the output signal Sout. In other words, the above identified sections (the constant signal level are not more than one clock cycle) in the input signal Sin are regarded as noises and the result of eliminating their noises is output as the output signal Sout.
FIG. 7 is a block diagram of another conventional digital noise filter circuit described in Patent Document 1. This is a modification of FIG. 5. This circuit includes DFFs 52, 54 and 56 arranged in a manner similar to the DFFs 12, 14 and 16 described above. A DFF 57 is connected to the output side of the DFF 56 and the width of noise removal is extended to less than three cycles. Patent Document 1 states that the width of noise removal may be made four cycles or greater in accordance with frequency of occurrence, etc.    [Patent Document 1]    Japanese Patent Kokai Publication No. P-P2004-200837A